In a mobile telecommunication system the received signal envelope may exhibit a very large dynamic range. A gain control is therefore required in the receiver to adjust the signal amplitude at the input of the analog-to-digital converter (ADC). The automatic gain control should control the signal amplitude to avoid or limit saturation of the analog-to-digital converter, and at the same time, ensure an efficient exploitation of the ADC dynamic range.
As reported in the standard technical literature, the AGC loop adjustment is based on the measurement of the received signal power. This measurement can be effected directly at the RF unit or after (i.e., downstream) the ADC. In a classical AGC implementation, the signal level is adjusted by multiplying the signal itself by a proper scale factor. This scale factor is calculated by measuring the received signal power over a certain interval.
In FIG. 1 a simplified block diagram of an AGC loop according to the prior art is shown. Such an AGC loop is designated by the reference numeral 10 and receives an input signal Sin, which corresponds to the received signal, as well as a reference digital signal Pref that is indicative of a reference power level.
The reference power signal Pref is fed to a summation node 11 along with a measured power signal Pmeas. In the summation node 11 the measured power signal Pmeas is added with a negative sign (i.e., subtracted) from the reference digital power signal Pref to obtain an error signal Perr. The error signal Perr is fed into a loop filter 12 with a transfer function F(z) that usually involves a FIR (Finite Impulse Response) filter, a gain factor and an integrator. The filter 12 produces a filtered error signal Pf, which is multiplied in a multiplying node 13 by the input signal Sin.
The output of the multiplying node 13 is sent to an analog-to-digital converter 14 that produces a digital output signal x(t) comprising a controlled output signal Sout of the loop 10. The controlled output signal Sout is also transmitted over a feedback branch back to the summing node 11. The feedback branch includes a power measurement block 15, which measures the power of the output signal Sout, thus generating the measured power signal Pmeas that is fed back to the summation node 11. The power measurement block 15 usually performs squaring and averaging operations over a certain time interval of the controlled output signal Sout to obtain the above mentioned scale factor for multiplying the input signal Sin.
The reference digital power signal Pref can be regarded as a steady state signal exempt from disturbances, whereas the power variations of the input signal Sin can be regarded as a source of disturbances. The loop shown in FIG. 1 performs a direct measurement of the power of the received signal. Such a direct measurement is, however, quite expensive in terms of required hardware resources and power consumption involved.